Embodiments of the inventive subject matter generally relate to the field of computers and, more particularly, to electronic design automation.
The design of integrated circuits (ICs), also referred to as “chips” or “microchips”, involve millions to billions of electrical components that need to be laid out and connected on a relatively small area of semiconductive material (e.g., the size of a fingernail or smaller). Before committing the circuit to fabrication, design engineers must determine the optimal configuration for the placement of the electrical components and for their connections (called “nets” or “wiring”). These design engineers use tools called electronic design automation (EDA) tools.
The portion of the design process for the IC that includes determining the optimal configuration for the placement and connection of the components is generally referred to as “physical synthesis.” The purpose of physical synthesis is to place the design for the IC (including the placement of components and wiring that connects the components), recognize delays and signal integrity issues introduced by the wiring, and fix the problems. If required timing criteria (e.g., timing constraints) of the design is no longer satisfied because of the positioning and wiring, then portions of the design need to be changed. For example, buffer amplifiers (buffers) and inverters may need to be added to certain portions of the design circuitry to improve signal transmission between the components and to prevent one portion of the design circuitry from interfering with a desired operation of another part of the design circuitry; a component or group of components may need to be reassigned to one of various metal layers; different logic gates may need to be changed in size, position, or power levels; gates and combinational logic may need to cloned; design elements may need to be modified to change gate threshold voltage levels to improve a speed or frequency of a gate; and so forth.
Because the IC design is so complex, different portions of the IC design are separately worked on and modified during physical synthesis. Thus, any required change in one portion of the IC design can potentially affect portions of the IC design that were previously worked on. Therefore, stages of the physical synthesis may need to revisited and addressed in an iterative manner, using the EDA tools, until all timing criteria is satisfied (i.e., until the design closes on timing). Consequently, physical synthesis can be a time consuming and laborious process.